Gary D. Hachtel
Fabio Somenzi
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Logic Synthesis and Verification Algorithms
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Description
Logic Synthesis and Verification Algorithms
is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics.
Logic Synthesis and Verification Algorithms
is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
Specifications
Publisher
Kluwer Academic Publishers
Pub date
June 30, 1996
Pages
32
Theme
Electronics: circuits and components
Measurements
254 x 178 mm
EAN
9780792397465
Binding
Hardback / bound
Language
English